As semiconductors achieve higher levels of integration and ever faster switching speeds, metal wiring layers formed within the semiconductor devices are getting finer and using multiple layers. However, as the widths of the metal wiring layers are reduced, signal delays may occur due to a resistance and parasitic capacitance (RC) of the metal wirings, thus impeding high speed switching and processing in semiconductor devices. An increase in leakage currents may also occur, increasing power consumption.
To reduce such signal delays, copper wiring may be employed instead of aluminum wiring. However, with the trend towards narrower wiring, parasitic capacitance between wiring increases, so that signal delays may occur even using copper wiring. To reduce the problem of RC delays, a low-k interlayer insulating film may be used between the wirings. As semiconductor devices get finer, a lower dielectric constant may improve performance significantly.
An interlayer insulating film may be formed with a porous low-k material. However, this alternative creates another difficulty: the pores on the surface of the interlayer insulating film degrade the flatness of the surface, making it difficult to properly deposit a film over the interlayer insulating film. In particular, the porous interlayer insulating film degrades the integrity of the diffusion barrier layer, which allows a greater diffusion of copper through the barrier.